1. Field of Invention
The present invention generally relates to a level shift circuit and a control pulse shaping unit, and more particularly to a level shift circuit and a control pulse shaping unit in a source driver of LCD.
2. Description of Related Art
FIG. 1 is a circuit diagram of a conventional level shift circuit 100. The level shift 100 includes a plurality of transistors 101˜105. A low-voltage signal IN1 is inputted to the gate of the transistor 104 and an inverted low-voltage signal INB1 is inputted to the gate of the transistor 105. The transistor 104 and the transistor 105 are electrically connected to the transistor 102 and the transistor 103, respectively. The transistor 102 and the transistor 103 are cross-coupled to each other and are formed similar as clamping transistors. A control signal CTRL0 is inputted to a gate of the transistor 101. A voltage VDDA is coupled to the transistor 101 and a voltage VSSA is coupled the transistors 104,105. The transistors 102,103 are commonly coupled to a node n1. The node n1 includes voltage V1. The transistor 103 outputs a high-voltage signal OD51 and the transistor 102 outputs an inverted high-voltage signal ODB51.
FIG. 2 shows the signals in the level shift circuit 100 upon transition of the input signal IN1 from a high to a low logic state. The transition starts from the time T21. At time T21, the control signal CTRL0 goes high to turn off the transistor 101 so that the voltage V1 drops. The transistor 102 is turned on and couples the voltage V1 to its drain. Since the voltage level of the signal ODB51 should be high enough to turn off the transistor 103, the control signal CTRL0 slightly drops at time T22 to partially turn on the transistor 101 so that the levels of the voltage V1 and signal ODB51 start to rise at time T22. However, the level of the signal ODB51 will not rise to a level high enough to fully turn off the transistor 103 at the end of the transition (at time T23) if the level of the input signal IN1 is too low. For such a low input signal, when the control signal CTRL0 turns on the transistor 101, the partially turned on transistor 103 couples a high voltage to its drain, which turns off the transistor 102 and keeps the signal ODB51 stay at a relatively low level. Thus, the transistor 103 is turned on and the signal OD51 is pulled high, which means that the transition fails.